VMIC /通用电气发那科VMIVME-2511采用两个摩托罗拉MC68230并行接口/定时器(PI/Ts)和一个MC68153总线中断模块(BIM)来支持所有电路板功能。

VMIVME-2511能够处理四个中断请求。每个PI/T模块能够处理两个请求:一个端口中断请求和一个定时器中断请求。四个中断请求信号(两个来自1号PI/T，两个来自2号PI/T)连接到BIM，为两个PI/T模块提供完全中断支持。每个PI/T模块都有两个用户可编程的片上中断向量寄存器。

VMIVME-1160A-323

Features:
32 optical coupled digital inputs
Highly isolated
5 V to 48 VDC input range (depending on option)

VMIC VMIVME-1160/VMIVME-1160A is designed with standard State of State (COS) control and interrupt logic, capable of detecting any COS and providing byte level interrupt vectors. It integrates the MC68153 Bus Interrupter Module (BIM) and supports any of the seven levels of interrupts. Each input byte may have a unique interrupt vector generated on the COS in any bit of that byte. The board also has an interrupt enable register that allows byte by byte interrupts to be enabled. Input data can be accessed through D8 or D16 transmission. Any COS (positive or negative conversion) will generate an interrupt. After COS interruption, polarity is determined by reading the input port.

32 differential or single ended low-level analog input channels
Buffered high-level analog output
Isolation from VMEbus; 500 V DC

VMIVME-3413 (Figure 1) is a 32 channel signal conditioning board designed to accept low-level differential or single ended inputs directly from temperature and pressure sensors or any other low-level analog signal source. Although the VMIVME-3413 board can be used with any advanced analog multiplexer, it is specifically designed as a companion product for GE Fanuc embedded system 64 channel scanning A/D boards.

The VMIC/General Electric Fanuc VMIVME-5576 reflective memory interface allows up to 256 independent systems (nodes) to share data at a rate of up to 6.2 megabytes per second. Each reflective memory board can be configured with onboard SRAM ranging from 256 kilobytes to 1 megabyte. Local SRAM provides fast read access time to stored data. The write operation is stored in the local SRAM and propagated to other reflective memory nodes through a high-speed fiber optic data path. The data transmission between nodes is software transparent, so there is no need for I/O overhead. Send and receive FIFOs buffer data during peak data rates to optimize CPU and bus performance and maintain high data throughput.

Reflective memory also allows interrupting one or more nodes by writing byte registers. These interrupt signals (three levels, user-defined) can be used to synchronize system processes or to track any data that may be prior to this. Interrupts always follow data to ensure that data is received before the interrupt is answered. VMIVME-5576 does not require initialization unless interrupts are in use. If using interrupts, the vector and interrupt level must be written to the onboard register and the interrupt must be initiated.